Logic synthesis

Results: 291



#Item
141Logic synthesis / Physical design / Register-transfer level / Altera Quartus / Place and route / Application-specific integrated circuit / Integrated circuit design / Digital electronics / Semiconductor intellectual property core / Electronic engineering / Electronic design automation / Field-programmable gate array

Benchmarking Method and Designs Targeting Logic Synthesis for FPGAs Joachim Pistorius, Mike Hutton Altera Corp. 101 Innovation Drive San Jose, CA 95134 {jpistori,mhutton}@altera.com

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Source URL: www.bvsrc.org

Language: English - Date: 2007-04-20 22:36:42
142Boolean network / American International Group / Science / Economy of New York City / Electronics / Diagrams / And-inverter graph / Electronic design automation

Scalable Logic Synthesis using a Simple Circuit Structure Alan Mishchenko Robert Brayton EECS Department, University of California, Berkeley, CA 94720

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Source URL: www.bvsrc.org

Language: English - Date: 2006-05-01 19:34:13
143Electronic design / Integrated circuits / And-inverter graph / Field-programmable gate array / Logic synthesis / Logic gate / Sequential logic / Power optimization / CMOS / Electronic engineering / Electronic design automation / Digital electronics

Microsoft Word - power18.doc

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Source URL: www.bvsrc.org

Language: English - Date: 2009-07-10 18:57:40
144Digital electronics / Diagrams / Logic in computer science / And-inverter graph / Retiming / Logic synthesis / Formal verification / Combinational logic / Standard cell / Electronic engineering / Electronic design automation / Formal methods

Verification after Synthesis Alan Mishchenko Robert Brayton Department of EECS

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Source URL: www.bvsrc.org

Language: English - Date: 2006-05-01 19:34:23
145Logic in computer science / Mathematics / Formal methods / Computer memory / Binary trees / Retiming / Flip-flop / Sequential logic / Combinational logic / Theoretical computer science / Digital electronics / Electronic engineering

Sequential Rewriting and Synthesis Robert Brayton Alan Mishchenko EECS Department, University of California, Berkeley, CA 94720

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Source URL: www.bvsrc.org

Language: English - Date: 2007-04-23 21:49:16
146Digital electronics / Electronic design / Formal methods / And-inverter graph / Retiming / Logic synthesis / Automatic test pattern generation / Field-programmable gate array / Sequential logic / Electronic engineering / Electronics / Electronic design automation

Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Robert Brayton

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Source URL: www.bvsrc.org

Language: English - Date: 2006-05-01 16:05:11
147Electronics / Boolean algebra / Diagrams / Algebraic logic / And-inverter graph / Logic synthesis / Boolean function / Circuit / Topology / Electronic engineering / Electromagnetism / Electronic design automation

Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton X. Wang T. Kam Department of EECS

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Source URL: www.bvsrc.org

Language: English - Date: 2005-05-01 15:18:03
148Electronics / Diagrams / Boolean algebra / And-inverter graph / Canonical form / Logic synthesis / Circuit / Boolean function / Topology / Electronic engineering / Electromagnetism / Electronic design automation

Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton X. Wang T. Kam Department of EECS

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Source URL: www.bvsrc.org

Language: English - Date: 2006-02-27 20:55:14
149Logic synthesis / Cube / Circuit minimization / Boolean function / Function / C++ / Espresso heuristic logic minimizer / Mathematics / Electronic engineering / Boolean algebra

Unate Decomposition of Boolean Functions Alan Mishchenko∗ Portland State University Dept. of Electrical and Computer Engineering Portland, OR 97207, USA [removed]

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Source URL: www.bvsrc.org

Language: English - Date: 2001-05-09 03:54:08
150Algebraic logic / Mathematical logic / Models of computation / Digital electronics / Electronic design automation / Toffoli gate / Quantum gate / Canonical form / Logic synthesis / Logic gates / Electronic engineering / Theoretical computer science

Logic Synthesis of Reversible Wave Cascades Portland Quantum Logic Group Alan Mishchenko and Marek Perkowski Department of Electrical and Computer Engineering Portland State University Portland, OR 97207, USA

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Source URL: www.bvsrc.org

Language: English - Date: 2002-05-17 14:51:54
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